1. Field of the Invention
The present invention relates to an improvement of a method for burying low resistance material in a contact hole.
2. Description of the Related Art
Conventionally, in a case where a metal wire is connected to a diffusion layer in a semiconductor substrate, the following methods are used.
An insulating layer is formed on the entire surface of the semiconductor substrate. A contact hole is formed in the insulating layer. Then, a metal film is formed by a sputtering method. Thereafter, the metal film is patterned, thereby forming a metal wire. However, in a case where the above method is used, the elements are integrated. Then, the step coverage of the metal wire in the contact hole worsens if an aspect ratio of the contact hole increases.
In recent years, much attention has been paid to a method for burying low resistance material (e.g., polycrystalline silicon) in the contact hole, and such a method has been studied. In a case where polycrystalline silicon is buried in the contact hole, it is required that a large amount of impurities be doped in polycrystalline silicon and the resistance of polycrystalline silicon be decreased. Generally, the above impurities are doped in polycrystalline silicon by an ion-implantation. However, an extremely high accelerating voltage is needed in order to implant an ion into a deep portion in the polycrystalline silicon. Due to this, there is a problem in that cost of an ion implantation device increases.
In a case where a plurality of contact holes are formed, and the contact holes are different in the depth, it is difficult to implant the ion into polycrystalline silicon in the all contact holes at the same time. In other words, it is impossible to evenly implant the ion into the polycrystalline silicon in the contact holes. This is because the ion cannot reach to the lower portion of polycrystalline silicon in the deep contact holes if the accelerating voltage is included in the shallow contact holes. For this reason, it is impossible to reduce the resistance value of the polycrystalline silicon in the deep contact holes.
For example, Unexamined Japanese Patent Application No. 1-205525 discloses the following points. The disclosure will be explained with reference to FIGS. 1A to 1F.
First of all, as shown in FIG. 1A, an impurity region, for example, a source region 303 of a MOS transistor is formed in a semiconductor substrate 301. An interlayer insulating film, for example, a silicon oxidation film 302 is formed on the entire surface of the semiconductor substrate 301. In the silicon oxidation film 302, there is formed a contact hole 304 reaching to the source region 303. Next, as shown in FIG. 1B, a polycrystalline silicon film 305 is formed on the entire surface of the silicon oxidation film 302 to be thinner than the half width of the contact hole 304. Then, as shown in FIG. 1C, impurities are doped in the polycrystalline silicon film 305 in the contact hole 304, so that the resistance value of a polycrystalline silicon film 305a in the bottom portion of the contact hole is reduced. Next, as shown in FIG. 1D, impurities are applied onto a polycrystalline silicon film 305b in order to reduce the resistance value of the polycrystalline silicon film 305b in the side wall of the contact hole 304. Then, as shown in FIG. 1E, a polycrystalline silicon film 306 is formed on the polycrystalline silicon film 305 by a CVD method, so that the contact hole is completely buried. Next, as shown in FIG. 1F, the polycrystalline silicon films 305 and 306 are etched back, so that the polycrystalline silicon films 305 and 306 is left in only the contact hole 304. Also, impurities, which are applied onto the polycrystalline silicon film 305b of the side wall portion in the contact hole 304, are thermally diffused to reduce the resistance value of the polycrystalline silicon film 306 in the contact hole 304. Thereby, polycrystalline silicon having low resistance is buried in the contact hole. Thereafter, a metal wire 307 is formed on the polycrystalline silicon films 305 and 306, and the source region 303 and the metal wire 307 are connected to each other.
According to the above method, the polycrystalline silicon films 305 and 306 are formed in the contact hole 304. Since the polycrystalline silicon films are thin, impurities can be easily doped into the polycrystalline films 305 and 306.
However, since impurities are doped into the polycrystalline silicon film 305, a natural oxidation film is formed on the surface of the polycrystalline silicon film 305 before the polycrystalline silicon film 306 is formed. Moreover, in general, there is formed the natural oxidation film between the semiconductor substrate 301 and the polycrystalline silicon film 305. Therefore, in the semiconductor device, which is formed by the above-mentioned method, two high resistors are sandwiched between the source region 303 and the metal wire 307, so that the contact resistance value is increased.